Self-test device for memories, decoders, etc.

ABSTRACT

A self-test device for memory arrangements, decoders or the like for use during on-line operation, the word lines and/or the column lines of a memory matrix being connected to a check matrix. An error detector which generates an error signal if more than one line is activated simultaneously is connected to the check matrix. Since multiple word lines or column lines are activated in the decoder for most errors which occur, a simple self-test can be performed during on-line operation by this check matrix which can be implemented in a relatively simple and cost-effective manner.

FIELD OF THE INVENTION

1. Prior Art

The present invention relate to a self-test device for memoryarrangements, decoders or the like for use during on-line operation,means for checking a plurality of word lines being provided.

2. Background Information

IEEE Trans. on Computer-Aided Design, Vol. 9, No. 6, June 1990, pp.567-572, "A Realistic Fault Model and Test Algorithms for Static RandomAccess Memories," discusses techniques for off-line testing of memoryarrangements which are known. These techniques can also be used to someextent as a "built-in self-test"; however, due to the numerous requiredtest patterns and the destruction of the memory content, they can beused only conditionally for testing during routine operation ("quasion-line"). Furthermore, the required test length prohibits their use inthe on-line test.

In addition, "Defect and Fault Tolerance in VLSI Systems," in Koren,Plenum Press, New York, 1989 (Design of Fault-Tolerant DRAM with new onChip ECC--Mazumber, P.), discusses arrangements having coding of datawhich are known in which different codes are used. However, a coding ofthis sort prevents only a very small share of the possible hardwareerrors in the memory arrangement to be checked.

Finally, there are techniques in which the actual selected memory cellis determined via a ROM and its address is compared with the desiredaddress.

In particular, row and column addresses are read out and compared withthe input address in a self-checking checker. Techniques of this sortare known, for example, from "Self-checking Flash-EPROM," M. Nicolaidis,contribution to the JESSI SE 11 project, presentation in the lecture onSep. 16, 1992 in Grenoble (France), or from "Efficient ubistimplementation for microprocessor sequencing parts," M. Nicolaidis, June1990, publication of the Institute IMAG/TIM 3, 46 Avenue Felix Viallet,38031 Grenoble (France). However, these self-test devices are veryexpensive in terms of circuit technology and cover on their own only thedecoder errors.

Overall, the known self-test devices and techniques either respectivelycover on their own only very few possible errors, or are very expensivewith regard to the necessary hardware, or are very time-consuming suchthat they are not suitable for on-line operation.

SUMMARY OF THE INVENTION

The self-test device according to the present invention has, incontrast, the advantage that, for monitoring the word lines, only a1-out-of-n checker is used which, during on-line operation, delivers anerror message via an error detector if more than one word line is activesimultaneously. As a result, most error sources in the decoder aredetected, and this self-test can be performed at a very low cost and athigh speed. Practically all addressing errors can be detected, providedthat it is ensured, through the coding of the address with a suitablecode in conjunction with constructive design features (miles) and a codecheck, that a single error does not influence two word lines in theopposite direction. Also, it can be ensured through the choice of thedata code that a faulty code is detected if no word line is activated.

In one preferred refinement of the 1-out-of-n checker according to thepresent invention, each word line in the check matrix is connectedrespectively to gate terminals (control connections) of z switches of aswitching matrix by way of which z test lines, having a first potential(Vdd) applied to them, can be connected either to terminals(connections) at a second potential (Vss) or to a sensor line, whichalso has the first potential (Vdd) applied to it corresponding to thecoding of the re respective word line, the error detector beingconnected to the sensor line and designed as a current or voltagesensor. If two word lines are simultaneously active, the error detectoris connected to the second potential via two switches such that anincreased current or rather a change in the potential, can be sensed.

The switches of the switching matrix are expediently designed as FETtransistors, and the terminals at a second potential (Vss) are designedas ground terminals.

To increase the reliability of the checking, the check matrix itself isadvantageously checked by a checking device which tests the functioningof the switches in the switching matrix. All switches are sequentiallychecked, respectively, at larger intervals.

In one advantageous refinement of this checking device, the test linesin the checking device are connected to tristate drivers by way of whichin each case the test line connected to the switches to be checked andtriggered for this purpose can be connected either to the secondpotential (Vss) or to the sensor line corresponding to the switchcoding. In this manner, the functionality of all the switches can betested one after another.

In addition, means for checking supply lines which are arranged inparallel to the word lines and carry the first (Vdd) and/or the secondpotential (Vss) can be provided even more expediently. The checking ofthe supply lines having the second potential applied to them can takeplace similarly to the checking of the switches by the checking device.To check the supply lines having the first potential (Vdd) applied tothem, additional switches are provided for controllable connection ofthe supply lines carrying this first potential to the sensor line, theseswitches being controllable by the word lines and/or by additionalcontrol lines. Here, following the discharging of the sensor line by thechecking of the supply lines carrying the second potential forhigh-impedance output drivers of the checking device, the recharging ofthe sensor line following the turning-on of the additional switches ischecked.

If the self-test device is used with memory arrangements such as RAM orROM memories, then it is fitting to use a first check matrix for the rowlines and a second check matrix for the column lines.

Using the 1-out-of-n checker according to the present invention,addressing errors can be detected which lead to the activation ofmultiple word lines. Incorrectly applied addresses and word lines/columndecoder lines reversed by a single defect cannot be detected in thisprocess. In order to also detect these possible errors, the inputaddresses are coded and a code checker is provided for the purpose ofchecking. If the inverted and the non-inverted value of an address bitwere to change due to a single defect, the code checker and the1-out-of-n checker could not detect this. In order to record thispossible error also, the non-inverted lines branching off from theindividual address lines and the lines branching off and inverted by aninverter are set apart from one another without common branch points. Inthis manner, it is practically excluded that simultaneous interruptionsof two lines arise through a defect. The 1-out-of-n checker can thendetect a line interruption of this sort. If all gases connected to theselines have the same input threshold value, i.e., if all of these gates,including the code checker, toggle their output level at the samevoltage level, then short-circuits between two lines can also bedetected. Since it is not always possible to meet thins requirementdimensioning specifications are given for the input inverters of theaddress lines, for the decoder gates and for the code checker by way ofwhich an error is detected either in the code checker or in the1-out-of-n checker for short-circuits between inverted and non-invertedaddress lines.

Even greater reliability can be achieved by connecting both inverters toa current monitoring device. Short-circuits can then be detecteddirectly via an increased current through the current monitoring device.

An even more advantageous solution is that from each address line thenon-inverted lines first branch off, set apart from one another andwithout a common branch point, the inverter for the inverted lines whichbranch off is connected into the address line, and the inverted linesbranch off from the inverted area of the address line set apart from oneanother and without common branch points. Using these tighter designrules, it is possible to use, instead of the 1-out-of-n checker, asimpler neighbor checker which checks only whether two word lines whichare assigned neighboring addresses are active simultaneously. A neighborchecker of this sort is known, for example, from "Error Detecting Codes,Self-checking Circles and Applications," J. Wakerly, Elsevier,North-Holland, 1978.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a memory arrangement having a rowdecoder and a column decoder.

FIG. 2 shows depiction of a 1-out-of-n checker.

FIG. 3 shows a schematic depiction of a checking device for the1-out-of-n checker.

FIG. 4 shows a circuit diagram of a ROM row for checking a prechargeline, the read amplifier (memory sense amplifier) and the read signalsof the memory arrangement.

FIG. 5 shows a modified 1-out-of-n checker for additional checking ofsupply lines arranged in parallel to the word lines.

FIG. 6 shows a geometric arrangement of non-inverted and inverted linesbranching off from an address line.

FIG. 7 shows a geometric arrangement of non-inverted and inverted linesbranching off from an address line having an additional currentmonitoring device.

FIG. 8 shows a further exemplary embodiment of a geometric arrangementof inverted and non-inverted lines branching off from a single addressline.

FIG. 9 shows a further exemplary embodiment of a geometric arrangementof inverted and non-inverted lines branching off from a single addressline having an additional current monitoring device.

FIG. 10 shows a schematic depiction of a gate implemented using staticCMOS technology.

DETAILED DESCRIPTION OF THE INVENTION

The memory arrangement shown in FIG. 1 could be a RAM memory, forexample, and consists in a manner known per se of a memory matrix 10, arow decoder 11 connected thereto and a comparably connected columndecoder 12. The column decoder is connected via a memory sense amplifier13 and a signature checker 14 to a data bus 15 for inputting (readingin) and outputting (reading out) data. An address bus 16 of width y+zbits, of which z bits are used for word line selection and y bits forcolumn selection, is connected to the row decoder 11 and the columndecoder 12 in order to be able to select n=2^(z) row addresses andp=2^(y) column addresses. Thus, the row decoder 11 is connected to thememory matrix 10 in a manner not further described via n row or ratherword lines and the column decoder 12 via m×p (m=bit width of the dataword) column lines. A 1-out-of-n checker 17 is assigned to the n wordlines of the memory matrix 10 and a corresponding 1-out-of-p checker isassigned to the p column lines which are generated in the column decoder12.

The 1-out-of-n checker 17 is shown in greater detail in FIG. 2. For thesake of simplicity, only the two word lines i and j are shown out of then row lines or rather word lines. The word lines extend in parallel intoa switching matrix 19, in which z test lines 20 run perpendicularly tothe n word lines. Outside of the switching matrix 19, another sensorline 21 runs in parallel to the test lines 20. The test lines 20 and thesensor line 21 have a first potential Vdd applied to them by aprecharging device 22. Each word line is coded differently by FETtransistors, it being possible for the coding to correspond to theaddress bits of the respective word line in special cases. Each wordline triggers for this purpose z of these FET transistors in parallel;the transistors are connected to the z test lines 20. For codingpurposes, the respective FET transistor connects the test line either tothe sensor line 21 or to a terminal at a low potential Vss; this is theground terminal in the exemplary embodiment.

In the exemplary embodiment shown, the coding of the word line i has,for example, a 1 at the start and a 0 at the end. Thus, thecorresponding first FET transistor 23 assigned to the first test lineconnects this first test line 20 to the sensor line 21, whereas thelast, i.e., the z-th FET transistor 24 connects the z test line toground With the word line j, the reverse holds: there, the first FETtransistor 25 connects the first test line to ground and the last FETtransistor 26 connects the z test line to the sensor line 21.

The sensor line 21 is connected to a current sensor 27 which sensesindirectly, through a change in the potential on the sensor line 21,whether a current is flowing via the test lines 20 to the lowerpotential Vss (ground in the exemplary embodiment). Moreover, a checkingdevice 28 is connected to the z test lines 20 and the sensor line 21which is described in greater detail in conjunction with FIG. 3.

Since each word line is coded differently in the switching matrix 19,the sensor line 21, which is precharged to the potential Vdd, becomesdischarged if more than one word line is active. If, for example, bothword lines i and j are active, then a discharging of the sensor line 21takes place via the transistors 23 and 25 and also via the transistors24 and 26. Since each word line is coded differently, one transistorcombination inevitably arises which brings about this discharging fortwo active word lines. Due to the discharging, a current is detected bythe current sensor 27 and an error message is output in a manner notconsidered in further detail. This error message indicates to the userthat an error has occurred.

To check the column address, the comparably designed 1-out-of-p checker18 is used; the difference is that instead of n (triggered) word lines,p column lines are now checked.

In FIG. 3, the checking device 28 is illustrated in greater detail.Essentially, it consists of z tristate drivers 29, each tri-state driverbeing connected to one of the test lines 20. Moreover, the sensor line21 having the potential Vdd applied to it is connected to all tristatedrivers 29. On the control side, all tristate drivers 29 have a commoncheck signal P as well as individual check signals T1 to Tz applied tothem.

Using this checking device 28, the functionality of each of the FETtransistors 23-26 in the switching matrix 19 is checked one afteranother, this test being executable both after a read/write access forthe addressed word line (single columns or all one after another) orcompletely in longer time intervals during an interruption in theoperation of the memory arrangement.

The checking of the transistors 23,26 connected to the sensor line 21will be explained using the example of transistor 23. First, testsignals P and T1 are generated by way of which the first test lineconnected to the transistor 23 is connected to the low potential Vss.Then, a control signal is applied to the word line i. If the transistor23 functions properly, it pulls the potential of the sensor line 21 toVss in this process so that the current sensor 27 is triggered. Here,this triggering acts as a confirmation signal for the proper functioningof this transistor 23.

The checking of the transistors 24,25 connected to ground will beexplained using the example of transistor 24. By way of correspondingcheck signals P and Tz, the z test line is connected to the sensor line21. If a signal is now applied to the word line i, the transistor 24,again assuming it is functioning properly, pulls the potential of thesensor line 21 to Vss so that the current sensor 27 is triggered. Inthis manner, all transistors can be checked one after another. Thenecessary check signals P and T, as well as the corresponding signals onthe word lines, are generated by a signal sequence controller, notshown, or rather by a microcomputer, not shown. The entire 1-out-of-nchecker is tested using n×z check steps. The checking of the 1-out-of-pchecker 18 can be handled in parallel.

A ROM row 30 shown in FIG. 4 can be used additionally duringinterruptions in the operation to check the precharge line for thememory matrix 10, the memory sense amplifiers 13, the read signals andthe inactivity of the write signals. In the exemplary embodiment, only asingle ROM row 30 is shown Which consists of four FET transistors 31which can be triggered via a common control line 32. Out of the sixcolumn lines shown, three can be connected--via three of the FETtransistors 31--to ground, whereas the sensor line 21 can be connectedto ground by way of the fourth FET transistor 31. The p column lines(six of which are shown) are precharged to the potential Vdd by aprecharging device 33. Three of the column lines are pulled down to thepotential Vss by a signal on the control line 32. In this process, adifferent data word is activated in each column by this ROM row 30 inorder to test the proper triggering of the column decoder and thecorrect functioning of the memory sense amplifier as will as the outputstages. Naturally, several such ROM rows having different coding canalso be provided, the data words specified by these ROM rows notnecessarily having to be code words for the case where the data arestored in the memory in an encoded state. Besides individual checking ofa column, it is also possible to read out all ROM data words one afteranother in a fixed order and to compare a signature formed therefromwith a stored desired signature. This takes place in the signaturechecker 14 shown in FIG. 1.

Normally, the Vdd and Vss supply lines in the memory matrix 10 are runin parallel to the bit lines (columns). By way of constructive designfeatures and the bit allocation of the matrix, it is to be assured thatthe same supply lines are not used for multiple bits of the same dataword. This decoupling is to be carried on consistently all the way tothe output stages of the memory arrangement. Common-mode errors due toinfluences of the supply voltage lines in the matrix are avoided in thismanner. A column-by-column supply is assumed, and the column decoder 12selects the data bits for each bit location in the same sequence.

If, in the special case, supply lines are to be run in parallel to theword lines, then checking by way of the circuit shown in FIG. 5 becomespossible. This circuit corresponds for the most part to the one shown inFIG. 2; components which are identical or which have an identical effectare provide with the same reference numbers and are not described again.A modified 1-out-of-n checker 17' is the result. In contrast to FIG. 2,two Vss lines as well as two Vdd lines are now run in parallel to theword lines i and j (and, also in parallel to the remaining word linesnot depicted). Moreover, a Vss lines is run to the checking device 28.Each Vdd line is connected to the sensor line 21 via the seriesconnection of the switching (connection) paths of two FET transistors34,35 or rather 36,37. The FET transistors 34,36 are controlled by theword lines i or rather j and the FET transistors 35,37 are controlledjointly by a control line 38.

In addition to the checking of the word lines according to FIG. 2, acheck of the Vdd or Vss lines is also possible. The Vss lines are alsochecked all the way up to a branch point if the checking device 28 isactivated following error-free word selection. This takes place duringthe checking of the transistors 24 and 25. If the branch point is at thestart of the memory matrix 10, then the entire row is also checked forinterruption of the Vss or rather ground line. Since there is notransistor on the ground line for the word line with the address "1111 .. . 1", this word line can also be checked by connecting it to theground terminal of the checking device 28, i.e., the ground terminal ofthe tristate drivers. In addition, the Vdd lines can also be tested. Forthis purpose, in each case after the Vss test (discharged sensor line21) for high-impedance tristate drivers 29 of the checking device 28,the control line 38 is activated and the recharging of the sensor line21 via the transistors 34,35 or rather 36,37 (depending on whether theword line i or j is activated) is checked.

The basis for the checking of the memory arrangement, or rather the wordlines and the column lines, up until now has been the assumption thatone or more word lines, or rather column lines, are additionallyactivated by an error in the row decoder 11 or column decoder 12. Thismethod cannot detect errors which are based on an incorrectly appliedaddress and on a reversal of word lines/column lines caused by a singledefect. To detect errors of this sort, the input address is coded, forexample, using a parity bit, a check of this code being handled by acode checker which can, for example, be included in the decoder. Inaddition, certain geometric precautions should be undertaken in order toprevent the inverted and the non-inverted value of an address bit fromchanging due to a single error without the code checker of the addressbeing able to note this change. This is achieved using the arrangementshown in FIG. 6.

For the sake of simplicity, only a single address line Ai is shown,which forms, via the input inverter 43, the address line Ai which, alongwith other address lines not shown, is fed to a code checker 39 in orderto check the coding of the input address. In this manner, it can bedetected if the applied address is incorrect. A non-inverted line 40 anda line 42 which is inverted using an inverter 41 branch off of thisaddress line Ai. These lines then branch off again in a known manner andrun to the gates of the row decoder 11 or column decoder 12. Thenon-inverted line 40 and the line to the inverter 41 are maintained atsuch a great distance from one another that a (point) defect cannotjointly influence them such that both can take on another potential thanthe line to the decoder 39, or such that this is at least unlikely.Here, star-shaped branches are ruled out, i.e., these two lines 40,42are branched off from distinct points which are set apart from oneanother on the address line Ai.

The inverters 41 and 43 and the gates not shown on the branched lines 40and 42 as well as the code checker 39 are dimensioned such that, forexample, if a short-circuit occurs between the lines 40 and 42, allgates not shown which are connected on these lines 40 and 42 and thecode checker 39 sense the same logical level if exactly one input signalis not at high (Vdd) or low (Vss) potential. The gates not shown whichare connected on the lines 40 and 42 as well as the code checker 39 andthe inverters 41 and 43 can be implemented, for example, usingconventional static circuit technology with complementary FETtransistors according to FIG. 10 (CMOS technology). In this technology,the P-channel branch 45 connects a current between the upper potentialVdd and the output 48 if the relevant inputs--here, only an input 47 isshown--are at low potential (Vss). In contrast, the N-channel branch 46carries a current between the output 48 and the low potential (Vss) ifthe relevant inputs--here, shown as input 47--have a high potential(Vdd).

If all gates directly connected to the lines 40 and 42, i.e., the gatesnot shown and the gates in the code checker, are implemented, forexample, such that only a single path exists in the N-channel branch 46from the output 48 to the low potential Vss and this path is dimensionedby the size of the transistors such that upon charge reversal of theoutput 48 from the high potential Vdd, more current flows than uponcharge reversal of the output 48 from the low potential Vss throughexactly one arbitrary path in the P-channel branch 45 for other inputcondition 47, then the condition must hold for the inverters 41 and 43that the transistors in the P-channel branch 45 supply more current atthe start of the charge reversal of the output 48 from the low potentialVss than the transistors in the N-channel branch 46 at the start of thecharge reversal of the output 48 from the high potential Vdd. Thiscondition is to be implemented similarly for all inverters 41 and 43with all address bits Ai, just as the same dimensioning specificationmust hold for all gates not shown on the lines 40 and 42 as well as thecode checker 39 for all address bits Ai.

Using the arrangement shown in FIG. 6, it is ensured that in general,only one line can be disconnected by a point defect or short-circuitedin the described manner such that as a result of this error, more thanone word line or no word line is activated which again can be detectedby the 1-out-of-p checker 17, 17'.

Using the arrangement shown in FIG. 7, short-circuits between the linescar be detected with even greater reliability. Both inverters 41,43 areconnected to a current sensor 44. If a short-circuit now occurs betweenan inverted line 42 and a non-inverted line 40, the current sensor 44senses an increased current draw by the inverters 41,43 since theyoperate against one another on the output side. This increased currentvalue which is sensed then leads to an error message. The current sensorcan be assigned to the line to the upper potential (Vdd) or to the lowerpotential (Vss).

FIG. 8 shows another alternative geometric configuration. Here, theinverter 41 is connected into the address line Ai, this being betweenmultiple branches of non-inverted lines 40 and multiple branches ofinverted lines 42. Both the inverted lines 42 as well as thenon-inverted lines 40 are set apart among one another and have in eachcase their own branch points from the address line Ai which are also setapart from one another. The gates not shown which are connected to thelines 40 and 42 and the directly connected gates of the code checker 39on the one hand and the inverters 41 and 43 on the other hand aredimensioned for all address lines Ai as described for the circuit inFIG. 6. If these geometric rules are met, assuming single defects of alimited size, then either one word line/column line will becomeadditionally active of which the address will differ by exactly 1 bitfrom the desired address, or no word line/column line will becomeactive. Both are detected by the 1-out-of-n checker 17, 17' or ratherthe 1-out-of-p checker 18. Since only word lines/column lines which arecontiguous in terms of address can become active, then, instead of a1-out-of-n checker, a simpler neighbor checker can also be used, thisneighbor checker being as described in the prior art specified in theintroduction ("Error Detecting Codes"). Interruptions of the word lineor the precharge line are also detected. The neighbor checker not onlyrequires less circuit engineering expense than the 1 -out-of-n checker,but the required test expense for the power-on test is alsosignificantly lower, the power-on test being necessary to verify theinitial error-free operation.

In FIG. 9, the corresponding circuit is shown with the current sensor44, similar to FIG. 7.

The described self-test device requires for coding with one parity bitonly an additional overall expense in terms of chip area of approx. 15%.Of this, 12.5% is allotted to the coding (8-bit data word and one paritybit) for the 1-out-of-n checker for four kbyte RAM with 256 rows and 128columns (+16 columns of parity bits, +8 columns of checker ROM), for arow-to-area ratio RAM: ROM=10 additionally approx. 0.6%.

Added to this are test hardware and the controller with an additionalapprox. 1%, while the expense for the column checker, the row ROM, theadditional hardware and the controller amounts to a total of approx.0.8%. In contrast, the usage of two code bits would already mean anadditional expense of 25%, the error coverage being considerably worsewithout the additional measures described according to the invention.

It should also be noted that the described self-test device cannaturally also be used for a wide variety of memory arrangements such asread-write memory (RAM) and read-only memory (ROM, EPROM and the like).Moreover, this self-test device can also be used alone for decoders.

What is claimed is:
 1. A self-test device for checking a plurality oflines, comprising:at least one check matrix coupled to the plurality oflines and including at least one 1-out-of-n checker, the 1-out-of-nchecker including at least one sensor line; and at least one errordetector coupled to the check matrix, the error detector generating anerror signal when at least two of the plurality of lines are activatedsimultaneously.
 2. The self-test device according to claim 1, whereinthe 1-out-of-n checker further includes at least one test line inparallel with the sensor line, at least one switching matrix, theswitching matrix including a plurality of first switches, each firstswitch having a first control gate terminal and a plurality of firstterminals, each first control gate terminal coupled to a respective oneof the plurality of lines, at least one of the plurality of firstterminals coupled to a test line, the test line having a first potential(Vdd), and at least one of the plurality of first terminals furthercoupled to at least one of a second potential (Vss) and the sensor line,the sensor line having the first potential (Vdd).
 3. The self-testdevice according to claim 2, wherein the plurality of first switches areFET transistors.
 4. The self-test device according to claim 2, whereinthe second potential (Vss) is ground.
 5. The self-test device accordingto claim 2, wherein the 1-out-of-n checker further includes at least onechecking device, the checking device coupled to the test line and to thesensor line, the checking device checking a functioning of the pluralityof first switches of the switching matrix.
 6. The self-test deviceaccording to claim 5, wherein the plurality of first switches of theswitching matrix are checked sequentially.
 7. The self-test deviceaccording to claim 5, wherein the checking device includes at least onetri-state driver, the tri-state driver coupled to the test line and toat least one of the second potential (Vss) and the sensor line.
 8. Theself-test device according to claim 5, wherein the 1-out-of-n checkerfurther includes a plurality of supply lines and at least one supplyline checker, the plurality of supply lines being in parallel with theplurality of lines, the plurality of supply lines having at least one ofthe first potential (Vdd) and the second potential (Vss), the supplyline checker being coupled to the plurality of supply lines.
 9. Theself-test device according to claim 8, wherein the supply line checkerincludes a plurality of second switches, each second switch having asecond control gate terminal and a plurality of second terminals, eachsecond control gate terminal coupled to a respective one of theplurality of lines, the plurality of second terminals further coupled tothe plurality of supply lines, the plurality of supply lines having thefirst potential (Vdd).
 10. A self-test device for checking a pluralityof lines, comprising:at least one check matrix coupled to the pluralityof lines, the plurality of lines including at least one of row lines andcolumn lines; at least one error detector coupled to the check matrix,the error detector generating an error signal when at least two of theplurality of lines are activated simultaneously; and a plurality ofaddress lines for transporting coded input addresses, at least one codechecker, and at least one inverter, the plurality of address bus linesincluding at least one first address line carrying a non-inverted signaland at least one second address line carrying an inverted signal, theaddress lines being coupled to the code checker, to the inverter, and tothe plurality of lines, the plurality of address lines being set apartfrom one another without common branch points, the error detectorgenerating the error signal when at least two of the plurality of linesassigned to neighboring addresses are activated simultaneously.
 11. Theself-test device according to claim 10, further comprising at least onememory matrix, the memory matrix coupled to the check matrix, the checkmatrix including at least one row check matrix for checking row linesand at least one column check matrix for checking column lines, the rowcheck matrix being coupled to the memory matrix and the column checkmatrix being coupled to the memory matrix.
 12. The self-test deviceaccording to claim 11, further comprising at least one memory senseamplifier, a plurality of precharge lines, at least one control line,and at least one ROM row, the ROM row checking at least one of theprecharge lines, the memory sense amplifier and read signals duringinterruptions in a test mode operation, the ROM row being coupled to theat least one of the precharge lines and to the control line.
 13. Theself-test device according to claim 12, wherein the memory matrixincludes one of a read-only memory and a read-write memory.
 14. Theself-test device according to claim 12, wherein the ROM row includes atleast one third switch, the third switch being coupled to the controlline.
 15. The self-test device according to claim 10, wherein the atleast one inverter includes a plurality of inverters, and furthercomprising at least one current monitoring device, the currentmonitoring device being coupled to the address lines and to theinverters, each of the address lines being coupled to a respective oneof the plurality of inverters.
 16. The self-test device according toclaim 10, wherein the at least one first address line includes aplurality of first address lines set apart from one another withoutcommon branch points, and wherein the at least one second address lineincludes a plurality of second address lines set apart from one anotherwithout common branch points.
 17. A self-test device for checking aplurality of lines, comprising:at least one check matrix coupled to theplurality of lines, the plurality of lines including at least one of rowlinks and column lines; at least one error detector coupled to the checkmatrix, the error detector generating an error signal when at least twoof the plurality of lines are activated simultaneously; at least onememory sense amplifier; plurality of precharge lines; at least onememory matrix, the memory matrix coupled to the check matrix, the checkmatrix including at least one row check matrix for checking row linesand at least one column check matrix for checking column lines the rowcheck matrix being coupled to the memory matrix and the column checkmatrix being coupled to the memory matrix, the memory matrix includingone of a read-only memory and a read-write memory, the memory matrixincluding a plurality of memory cells for storing bits of a memory word,at least one of the precharge lines having a first potential (Vdd) andat least one other of the precharge lines having a second potential(Vss), the plurality of memory cells being coupled to the at least oneof the precharge lines and to the at least one other of the prechargelines, outside of the memory matrix; at least one control line; and atleast one ROM row, the R0M row checking at least one of the prechargelines, the memory sense amplifier and read signals during interruptionsin a test mode operation, the R0M row being coupled to the at least oneof the precharge lines and to the control line.
 18. The self-test deviceaccording to claim 17, further comprising means for detectinginterruption of the precharge lines within the memory matrix.
 19. Theself-test device according to claim 10, wherein one of the checkers andthe check matrix detects a short-circuit between at least two of theplurality of address lines.
 20. The self-test device according to claim1, wherein the self-test device is one of a memory arrangement and adecoder.